【電子所專題演講公告】

電子所將於12/17(一)邀請立聯合醫院中興院區詹佳真醫師蒞臨演講，演講資訊如下：

講者：市立聯合醫院中興院區詹佳真醫師
講題：壓力與人生
時間：13:30-14:30
地點：博理113室

現任：臺北市立聯合醫院中興院區精神科主治醫師

專業領域：1.恐慌症、焦慮症、憂鬱症
　　　　　2.團體心理治療
　　　　　3.女性成長、個別心理治療

學歷：私立中山醫學院醫學系畢業

經歷：臺北市立療養院住院醫師、總醫師、主治醫師、臺北市立中興醫院精神科主任

【公文公告】

【邀請演講公告】

演講者：Dr. Chung-Jen Chen（Honeywell International）
演講日期: 12/18(二) 10:00-11:00
演講地點: 博理館201室
講題：Loop-Closure Signal Processing Techniques for the Interferometric Fiber-Optic Gyroscopes

Interferometric fiber optic gyroscope (IFOG) is an optical rotation sensor with unique advantages in low component count, high reliability and potential for low cost. After 30 years of research and development since its inception in 1976, IFOG has gradually been used in many real world applications requiring high precision and long mission life such as inertial guidance, attitude control, and platform stabilization in space, air, surface, and submerged environment.  This delicate optical instrument relies on the loop-closure signal processing electronics to increase its dynamic sensitivity range while maintaining full capability of its optical performance.  In this presentation, several signal processing techniques will be discussed to reveal their functions and limitations to the gyroscope.

Bibliography:

Dr. Chung-Jen Chen received his B.S. and M.S. in physics from National Tsing-Hua University, Hsinchu, Taiwan, in 1990 and 1992, respectively, and his Ph.D. in materials science and engineering from the University of Minnesota, Minneapolis, in 1996.  In 1997, Dr. Chen joined Honeywell International, where he is currently a Staff Scientist in the Aerospace division in Clearwater, Florida.  His research activities focus on the development of precision rotation sensors and the related systems.  Prior to Honeywell, Dr. Chen was a research member at IBM T.J. Watson Research Center at Yorktown Heights, New York from 1994 to 1996 through an IBM Cooperative Fellowship.  Dr. Chen holds 7 US patents and 5 in pending. He received numerous Technical Achievement Awards from Honeywell.

【資工系邀請演講公告】

Speaker: Hsien-Hsin S. Lee, Georgia Tech
Time: 02:20pm, December 21 (Fri), 2007
Place: Room 103, CSIE building
Title: POD: a Heterogeneous Many-Core Platform Using a 3D-integrated Acceleration Layer

Abstract:
With the continuing trend of process technology advancement, to integrate 10 to 100 billion transistors on a reasonable die area is becoming feasible in the near future. Researchers envision a microprocessor packed with hundreds or even a thousand transistors is looming on the horizon. To make such designs viable,nonetheless, one fundamental physical limit --- power consumption, must be addressed. In this talk, we will argue that current symmetric, homogeneous many-core processors integrated with a MIMD manner, even though are easier to implement by replication, they are, however, inappropriate for a scalable solution from the perspective of energy- and area-efficiency for high performance computing.  In search for an alternative, I will discuss a new many-core architecture that we are currently developing at Georgia Tech with Intel Research called Parallel-On-Demand (or POD). POD, designed around the goal of optimized power/performance/area scalability, leverages ideas from massive parallel processing for future on-die many-core architectures. POD integrates a snap-on broad-purpose performance acceleration layer enabled by the emerging 3D die stacking technology to facilitate flexibility. On the other hand, we advocate the use of simplified point-to-point communication interconnects to keep the overall power on leash.  I will also discuss its programming model, design space, complexity-effectiveness, and early simulation results. Additionally, a few challenges in the incoming many-core era will be presented to boggle your minds. 

Short Bio:
Hsien-Hsin Sean Lee (李憲信) is an Assistant Professor of the School of Electrical and Computer Engineering at Georgia Institute of Technology. He received his PhD degree in computer science and engineering from the University of Michigan at Ann Arbor. His main research interests include computer architecture, low-power circuits, information security, and enabling techniques for the emerging 3D-ICs.  Prior to joining academia, he was a senior processor architect at Intel Corporation (1995-2001) working on Pentium Pro, Pentium III, and Itanium processor research. Later, he was the architecture manager of StarCore DSP Center (2001-02), a joint design center of Agere systems and Motorola Inc. Dr. Lee's doctoral thesis was awarded the Horace H. Rackham School Distinguished Dissertation Award at the University of Michigan. He has co-authored three papers that won the Best Paper Awards at MICRO-33, CASES-04, and IBM PAC2.  Dr. Lee received the Department of Energy Early CAREER PI Award in 2005, the 2006 ECE Outstanding Jr. Faculty Member Award at Georgia Tech, and the NSF CAREER Award in 2007. Dr. Lee holds 4 U.S. patents. He is a member of Tau Beta Pi and the ACM, and a senior member of the IEEE.